Semiconductor integrated circuit device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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Details

C257S758000, C257S183000, C257S197000, C257S762000, C257S766000

Reexamination Certificate

active

07554202

ABSTRACT:
Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

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Lee et al., An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI), 1996, Symposium on VLSI Technology Digest of Technical Papers, pp. 158-159.

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