Sensing of memory cells in a solid state memory device by...

Details Sensing of memory cells in a solid state memory device by... Sensing of memory cells in a solid state memory device by...

2007-11-20

2009-10-27

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S233100, C365S233110, C365S185140

Reexamination Certificate

active

07609560

ABSTRACT:
In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to which the target memory cell is coupled. A fixed unit of charge is removed from the charged bit line. The bit line is sensed by sense amplifiers to determine the read voltage (i.e., threshold voltage) applied to a word line coupled to the target cell in order to turn on the target cell. The threshold voltage is indicative of the analog voltage stored on the target memory cell.

REFERENCES:
patent: 2008/0165585 (2008-07-01), Surico et al.
patent: 2008/0247254 (2008-10-01), Nguyen et al.
patent: 2009/0003069 (2009-01-01), Lee et al.
Tanaka, Tomoharu, “Multiple Level Cell Memory Device With Improved Reliability,” (22 pages including drawings) U.S. Appl. No. 12/059,572, filed Mar. 31, 2008.

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