Electronic device including a gated diode

Details Electronic device including a gated diode Electronic device including a gated diode

2008-08-29

2009-08-11

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S104000, C257S133000, C257S330000

Reexamination Certificate

active

07573114

ABSTRACT:
An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

REFERENCES:
patent: 4859623 (1989-08-01), Busta
patent: 5532486 (1996-07-01), Stanchina et al.
patent: 5689127 (1997-11-01), Chu et al.
patent: 5804848 (1998-09-01), Mukai
patent: 6011725 (2000-01-01), Eitan
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6300182 (2001-10-01), Yu
patent: 6330184 (2001-12-01), White et al.
patent: 6355961 (2002-03-01), Forbes
patent: 6372559 (2002-04-01), Crowder et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6414356 (2002-07-01), Forbes et al.
patent: 6424001 (2002-07-01), Forbes
patent: 6433609 (2002-08-01), Voldman
patent: 6458662 (2002-10-01), Yu
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6531350 (2003-03-01), Satoh et al.
patent: 6566682 (2003-05-01), Forbes
patent: 6583469 (2003-06-01), Fried et al.
patent: 6642115 (2003-11-01), Cohen et al.
patent: 6657252 (2003-12-01), Fried et al.
patent: 6686245 (2004-02-01), Mathew et al.
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6720216 (2004-04-01), Forbes
patent: 6768158 (2004-07-01), Lee et al.
patent: 6800905 (2004-10-01), Fried et al.
patent: 6846734 (2005-01-01), Amos et al.
patent: 6903967 (2005-06-01), Mathew et al.
patent: 6936895 (2005-08-01), Manna et al.
patent: 6969656 (2005-11-01), Du et al.
patent: 7098502 (2006-08-01), Mathew et al.
patent: 7192876 (2007-03-01), Mathew et al.
patent: 7301741 (2007-11-01), Khazhinsky et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2005/0077577 (2005-04-01), Manna et al.
patent: 2005/0167709 (2005-08-01), Augusto
patent: 2006/0022264 (2006-02-01), Mathew et al.
patent: 2006/0091490 (2006-05-01), Chen et al.
patent: 101 25 967 (2002-07-01), None
patent: 00/21118 (2000-04-01), None
Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electronic Device Letters, Mar. 1987, vol. EDL-8, No. 3, pp. 93-95.
Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, Dec. 2000, vol. 47, No. 12, pp. 2320-2325.
Lee et al., “Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI,” IEEE Electron Device Letters, 2000, pp. 1-3 and 208-209.
Choi et al., “Sub-20 nm CMOS FinFET Technologies,” 0-7803-7052-X/01 IEEE, 2001, pp. 1-4.
Fossum et al., “Extraordinarily High Drive Currents in Asymmetrical Double-Gate MOSFETs,” Superlattices and Microstructures, vol. 28, No. 5/6, 2000, pp. 525-530.
Kim et al., “Double-Gate CMOS: Symmetrical-Gate Devices,” IEEE Transaction on Electron Devices, vol. 48, No. 2, Feb. 2001, pp. 294-299.
Tanaka et al., “Ultrafast Operation of Vth-Adjusted P+-N+ Double-Gate SOI MOSFET's,” IEEE Electron Devices Letters, vol. 15, No. 10, Oct. 1994, pp. 386-388.
Yu et al., “FinFET Scaling to 10 nm Gate Length,” IEDM, 2002, pp. 251-254.
Singer et al., “Dual Gate Control Provides Threshold Voltage Options,” Semiconductor International, Nov. 1, 2003, pp. 1-2.
Denton et al., “Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET With An Isolated Buried Polysilicon Backgate,” Proceedings 1995 IEEE International SOI Conference, Oct. 1995, pp. 135-136.
Tanaka et al., “Analysis of P+ Poly Si Double-Gate Thin-Film SOI MOSFETS,” IEEE, 1991, pp. 26.6.1-26.6.4.
Russ et al., “ESD Evaluation of the Emerging MuGFET Technology,” 2005 EOS/ESD Symposium, ESD Association, pp. 1-10.
PCT/US2006/061312 International Search Report and Written Opinion.

Affiliated with

Also associated with

Rating

Electronic device including a gated diode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electronic device including a gated diode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electronic device including a gated diode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4079936