Architecture and method for NAND flash memory

Details Architecture and method for NAND flash memory Architecture and method for NAND flash memory

2008-04-22

2009-06-02

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185170

Reexamination Certificate

active

07542336

ABSTRACT:
A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitlines can be used at boundaries between even and odd sections of the array to further reduce floating gate coupling.

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