Excavating
Patent
1997-02-20
1999-06-15
Baker, Stephen M.
Excavating
371 376, 371 3712, H03M 1300
Patent
active
059129050
ABSTRACT:
The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs. The syndrome generator of the error-correcting decoder of the invention includes a plurality of Galois field multipliers which multiply the coefficients for calculating syndromes for inputting different code symbols in parallel from a plurality of input terminals. The syndrome generator also includes a Galois field adder and a shift register to obtain the predetermined syndrome generating polynomial. The syndrome generator can obtain the desired syndromes with shifts, the number of which is reduced according to the number of parallel inputs.
REFERENCES:
patent: 3452328 (1969-06-01), Hsiao et al.
patent: 4782490 (1988-11-01), Tenengolts
patent: 4899341 (1990-02-01), Tomimitsu
patent: 4979173 (1990-12-01), Geldman et al.
patent: 5107503 (1992-04-01), Riggle et al.
patent: 5107506 (1992-04-01), Weng et al.
patent: 5140596 (1992-08-01), Weldon, Jr.
patent: 5365529 (1994-11-01), Mester
patent: 5375127 (1994-12-01), Leak et al.
patent: 5699368 (1997-12-01), Sakai et al.
Whiting, D., "Bit-Serial Reed-Solomon Decoders in VLSI", 1985, Ph.D. Thesis 8501350, California Inst. of Technology, pp. 88-99, Dec. 1985.
Tomoko Matsushima "A Design of a High-Speed Reed-Solomon Codec LSI" pp. 103-106.
N. Glover, et al, "Practical Error Correction Design for Engineers", 2nd, ed., Data Systems Technology Corp., pp. 49, 50, 243-249.
Sakai Yasuyuki
Tokita Toshio
Yoshida Hideo
Baker Stephen M.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Error-correcting encoder, error-correcting decoder and data tran does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Error-correcting encoder, error-correcting decoder and data tran, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error-correcting encoder, error-correcting decoder and data tran will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-407470