Method for the production of an error correction parameter assoc

Details Method for the production of an error correction parameter assoc Method for the production of an error correction parameter assoc

1997-01-07

1999-06-15

Chung, Phung M.

Excavating

364746, G06F 1110, G06F 772

Patent

active

059129042

ABSTRACT:
Disclosed is a method for producing a binary error correction parameter H=2.sup.(m1+m2)*k mod N by means of a coprocessor having registers with at most m*k bits, N being a binary data element encoded on m1 words of k bits, m1 being an integer greater than m, m, m2 and k being non-zero integers, the coprocessor including a first register, a register, a third register and a fourth register, a subtraction circuit and comparison circuitry. The disclosure thus proposes a circuit and a method specially suited to the required computation without excessively increasing the size of the coprocessor.

REFERENCES:
patent: 5513133 (1996-04-01), Cressel et al.
patent: 5764554 (1998-06-01), Monier
French Search Report from French Patent Application 96 00692, filed Jan. 18, 1996.
IEEE Journal on Selected Areas in Communications, vol. 11, No. 5, Jun. 1, 1993, pp. 761-769, Arazi, B. "Double-Precision Modular Multiplication Based on a Single-Precision Modular Multiplier and a Standard CPU".

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