Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-10-15
2009-08-18
Donovan, Lincoln (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S543000
Reexamination Certificate
active
07576594
ABSTRACT:
A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal device10, the influence of the Early effect pertaining to the three-terminal device of a FET is reduced. In order to reduce the influence, control unit30is set for reducing the Early effect component caused by a three-terminal device. As a result, by controlling the potential of the second terminal (such as drain) of the device as a response to a first signal pertaining to the input signal received by the first terminal (such as gate) of the device, it is possible for the potential difference between the second terminal (drain) and the third terminal (such as source) of the device to be essentially constant.
REFERENCES:
patent: 4412186 (1983-10-01), Nagano
patent: 4462005 (1984-07-01), Kusakabe et al.
patent: 4629973 (1986-12-01), Voorman
patent: 4681441 (1987-07-01), Uchidoi et al.
patent: 4714845 (1987-12-01), Devecchi et al.
patent: 5045808 (1991-09-01), Taylor
patent: 5083051 (1992-01-01), Whatley et al.
patent: 5140279 (1992-08-01), Scott, III
patent: 5198782 (1993-03-01), Scott
patent: 5313089 (1994-05-01), Jones, Jr.
patent: 5365199 (1994-11-01), Brooks
patent: 5469104 (1995-11-01), Smith et al.
patent: 5654673 (1997-08-01), Shinohara
patent: 5774021 (1998-06-01), Szepesi et al.
patent: 6018269 (2000-01-01), Viswanathan
patent: 6054901 (2000-04-01), Nainar et al.
patent: 6177827 (2001-01-01), Ota
patent: 6246290 (2001-06-01), Morrish et al.
patent: 6396249 (2002-05-01), Itakura et al.
patent: 6407620 (2002-06-01), Hirayama
patent: 6426669 (2002-07-01), Friedman et al.
patent: 6545513 (2003-04-01), Tsuchida et al.
patent: 6573784 (2003-06-01), Gower et al.
patent: 6653891 (2003-11-01), Hazucha
patent: 6654066 (2003-11-01), Vu et al.
patent: 6661253 (2003-12-01), Lee et al.
patent: 6727729 (2004-04-01), Brooks et al.
patent: 6937104 (2005-08-01), Varadarajan et al.
patent: 6977490 (2005-12-01), Zhang et al.
patent: 7019580 (2006-03-01), Michalski
patent: 7385426 (2008-06-01), Wan et al.
patent: 2001/0043115 (2001-11-01), Barou et al.
patent: 2002/0093316 (2002-07-01), Fahrenbruch
patent: 2002/0175761 (2002-11-01), Bach et al.
patent: 2005/0057189 (2005-03-01), Kimura
patent: 2007/0103207 (2007-05-01), Huang
patent: 2008/0122519 (2008-05-01), Nowak
patent: 2008/0129326 (2008-06-01), Agarwal et al.
Viswanathan, T.L., CMOS Transconductance Element, proceedings of the IEEE, vol. 74, No. 1, Jan. 1986, pp. 222-224.
Brady III Wade J.
Donovan Lincoln
Hiltunen Thomas J
Patti John J.
Telecky , Jr. Frederick J.
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