Pipelined systolic array for matrix-matrix multiplication

Details Pipelined systolic array for matrix-matrix multiplication Pipelined systolic array for matrix-matrix multiplication

1984-08-10

1987-08-11

Williams, Jr., Archie E.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

046866450

ABSTRACT:
A digital data processor for matrix/matrix multiplication includes a systolic array of nearest neighbor connected gated full adders. The adders are arranged to multiply two input data bits and to add their product to an input cumulative sum bit and a carry bit from a lower order bit computation. The result and input data bits are output to respective neighboring cells, a new carry bit being recirculated for later addition to a higher order bit computation. Column elements of one matrix and row elements of the other are input to either side of the array bit-serially, least significant bit leading, for mutual counterpropagation therethrough with a cumulative time delay between input of adjacent columns or rows. Bit-level matrix interactions for product matrix computation occur at individual cells. Pairs of intercalated adder trees are connected switchably to the array to accumulate bit-level contributions to product matrix elements.

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