Devices and systems including the bit lines and bit line...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C267S251000, C267S251000

Reexamination Certificate

active

07638878

ABSTRACT:
A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases processing latitude, particularly the spacing between the bit lines which, with conventional processes, may strain photolithographic limits. A semiconductor device formed using the method, and an electronic system comprising the semiconductor device, are also described.

REFERENCES:
patent: 5680364 (1997-10-01), Lee
patent: 5757710 (1998-05-01), Li et al.
patent: 5835396 (1998-11-01), Zhang
patent: 6310800 (2001-10-01), Takahashi
patent: 6387759 (2002-05-01), Park et al.
patent: 6853023 (2005-02-01), Goebel et al.
patent: 6873007 (2005-03-01), Sugita et al.
patent: 2003/0085421 (2003-05-01), Takeuchi et al.
patent: 2004/0037113 (2004-02-01), Ooishi
patent: 2004/0051133 (2004-03-01), Sugita et al.
patent: 2004/0079988 (2004-04-01), Harari
patent: 2004/0108512 (2004-06-01), Iwata et al.
patent: 01/47019 (2001-06-01), None
patent: 2004/102666 (2004-11-01), None
Search Report and Written Opinion for International Application No. PCT/US2007/009282, 14 pages, Dec. 3, 2007.

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