Semiconductor memory device with memory cells each including...

Details Semiconductor memory device with memory cells each including... Semiconductor memory device with memory cells each including...

2006-12-20

2009-02-03

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S207000, C365S203000, C365S210130

Reexamination Certificate

active

07486565

ABSTRACT:
A semiconductor memory device includes a memory cell array, a bit line, a precharge circuit and a first sense amplifier. The memory cell array includes memory cells. The bit line connects commonly the memory cells in the same column. The precharge circuit applies a precharge potential to the bit line in reading data. The first sense amplifier amplifies data read onto the bit line. The precharge circuit determines the data read on the bit line using as a reference potential the precharge potential applied to the bit line by the precharge circuit.

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U.S. Appl. No. 11/445,302, filed Jun. 2, 2006, Toshiaki Edahiro.
Toru Tanzawa, et al., “Design of a Sense Circuit for Low-Voltage Flash Memories”, IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000, pp. 1415-1421.

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