Controlled ramp rates for metal bitlines during write...

Details Controlled ramp rates for metal bitlines during write... Controlled ramp rates for metal bitlines during write...

2007-10-16

2009-12-08

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185180, C365S185230

Reexamination Certificate

active

07630250

ABSTRACT:
Systems and methods that control the switching transition times or profile of a ramped voltage write signal used for programming or erasing at least a wordline of an array of multi-bit and/or multi-level flash memory cells are provided. In one embodiment, this goal is accomplished by applying a ramped or otherwise controlled profile write voltage to the flash memory cells in order to avoid disturb issues to the unselected (non-targeted) neighboring memory cells, which preserves the existing state of the neighboring cells while keeping the design as compact and manageable as possible yet maintains a high write speed. The systems and method are applicable to, and reliable for various memory technologies, since the size of the steps or other such functional transitions of the ramped voltage profile can be adjusted or trimmed to any level of resolution required.

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International Search Report for Application # PCT/US2008/079993 dated Jan. 22, 2009.

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