Erase verifying method of NAND flash memory device

Details Erase verifying method of NAND flash memory device Erase verifying method of NAND flash memory device

2007-12-29

2009-10-20

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185180, C365S185220, C365S185330

Reexamination Certificate

active

07606080

ABSTRACT:
In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory cell transistors. A second positive voltage is applied to source lines to which sources of the select transistors and the memory cell transistors are connected. An erased state of the memory cell transistor is verified according to whether charges accumulated in the first bit line are discharged.

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patent: 5995417 (1999-11-01), Chen et al.
patent: 7154787 (2006-12-01), Omoto
patent: 7272050 (2007-09-01), Han et al.
patent: 7333371 (2008-02-01), Hosono

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