Method and system to implement an improved floating point...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07552165

ABSTRACT:
Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are added together to produce a third mantissa. The third mantissa is normalized to produce a final mantissa. The third mantissa and the final mantissa are correctly rounded as a result of the act of adding, so that the final mantissa does not require processing by a follow on rounding stage.

REFERENCES:
patent: 5373461 (1994-12-01), Bearden et al.
patent: 5390134 (1995-02-01), Heikes et al.
patent: 5408426 (1995-04-01), Takewa et al.
patent: 5790445 (1998-08-01), Eisen et al.
patent: 6148314 (2000-11-01), Matheny et al.
patent: 6148316 (2000-11-01), Herbert et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and system to implement an improved floating point... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system to implement an improved floating point..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system to implement an improved floating point... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4067076

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.