Pulse or digital communications – Synchronizers
Reexamination Certificate
2005-08-11
2009-06-30
Phu, Phuong (Department: 2611)
Pulse or digital communications
Synchronizers
C375S376000, C375S371000, C327S145000
Reexamination Certificate
active
07555084
ABSTRACT:
The present invention performs a digital computation with a lower than worst-case-required clock period (i.e., a faster clock), and at the same time performs the same computation with a larger, worst-case-assumed, clock period (i.e., a slower clock) on a second system with identical hardware. The outputs from the computations are compared to determine if an error has occurred. If there is a difference in the two answers, the faster computation must be in error (i.e., a miscalculation has occurred), and the system uses the answer from the slower system. In one embodiment, the present invention utilizes two copies of the slower system that each run half as fast as the main system. However, the two copies produce results in the aggregate at the same rate as the main system, which is running at a much faster rate than possible without the invention. Hence the present invention improves performance (e.g., speed), albeit with more hardware. Advantageously, the present invention dynamically adapts to achieve the best performance possible under the actual operating conditions.
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Connolly Bove & Lodge & Hutz LLP
Phu Phuong
The Board of Governors for Higher Education, State of Rhode Isla
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