Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-05-12

2009-08-25

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S230060

Reexamination Certificate

active

07580316

ABSTRACT:
Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

REFERENCES:
patent: 6058065 (2000-05-01), Lattimore
patent: 6920058 (2005-07-01), Morikawa
patent: 7251184 (2007-07-01), Nakaya et al.
patent: 7379362 (2008-05-01), Abe et al.
patent: 2006/0221754 (2006-10-01), Abe
patent: 6176592 (1994-06-01), None

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