Low profile semiconductor package

Details Low profile semiconductor package Low profile semiconductor package

2006-10-19

2009-10-06

Chambliss, Alonzo (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With semiconductor element forming part

C257S686000, C257S687000, C257S690000, C257S777000, C257S784000, C257SE23031, C257SE23042, C361S772000, C361S774000, C361S813000

Reexamination Certificate

active

07598604

ABSTRACT:
A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of the first and second semiconductor elements are connected to the first and second connection terminals via bonding wires. A metal circuit board including the first and second connection terminals, and the first and second semiconductor elements are sealed by a sealing material such that parts of the respective connection terminals expose.

REFERENCES:
patent: 5723903 (1998-03-01), Masuda et al.
patent: 6133637 (2000-10-01), Hikita et al.
patent: 6303981 (2001-10-01), Moden
patent: 6380615 (2002-04-01), Park et al.
patent: 6476474 (2002-11-01), Hung
patent: 6552437 (2003-04-01), Masuda et al.
patent: 6555917 (2003-04-01), Heo
patent: 6677674 (2004-01-01), Nagao
patent: 6750080 (2004-06-01), Masuda et al.
patent: 6955941 (2005-10-01), Bolken
patent: 2002/0027266 (2002-03-01), Wada et al.
patent: 2005/0110127 (2005-05-01), Kanemoto et al.
patent: 2001-36000 (2001-02-01), None
patent: 2002-0061444 (2002-07-01), None

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