Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-10-25
2009-02-10
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233130, C365S196000, C365S190000, C365S208000, C365S207000, C365S227000
Reexamination Certificate
active
07489588
ABSTRACT:
A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
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Akiyama Satoru
Hanzawa Satoru
Kajigaya Kazuhiko
Sekiguchi Tomonori
Takemura Riichiro
Elpida Memory Inc.
Hitachi , Ltd.
Miles & Stockbridge P.C.
Tran Andrew Q
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