Emulation processor interconnection architecture

Details Emulation processor interconnection architecture Emulation processor interconnection architecture

2005-12-29

2009-06-30

Rodriguez, Paul L (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

C703S028000, C716S030000

Reexamination Certificate

active

07555423

ABSTRACT:
The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

REFERENCES:
patent: 5551013 (1996-08-01), Beausoleil et al.

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