Clock distribution for specialized processing block in...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

Reexamination Certificate

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C327S565000

Reexamination Certificate

active

07545196

ABSTRACT:
Clocks are distributed efficiently to regions of a specialized processing block in a PLD. Multiple clocks are selected from a larger universe of clocks and distributed to the specialized processing block, but the choices of clocks at the individual functional regions, or stages of functional regions, are less than fully flexible. In some cases, an entire region may use one clock. In another case, portions of a stage within a region that previously had been able to select individual clocks must use one clock for the entire stage. In another case, only a subset of the selected clocks is available for a particular region, but that subset is flexibly distributable within the region. In another case, a clock may be selectable for each stage of each functional region directly from the larger universe of available clocks, avoiding the need for circuitry to select the multiple clocks from the larger universe.

REFERENCES:
patent: 6028463 (2000-02-01), Albu et al.
patent: 7145362 (2006-12-01), Bergendahl et al.
patent: 7178075 (2007-02-01), Warnock et al.
patent: 2005/0242867 (2005-11-01), Ghia et al.
Altera Corporation, “DSP Blocks in Stratix® II ad Stratix® II GX Devices,”Stratix® II Device Handbook, vol. 2, pp. 6-1 through 6-34 (Feb. 2007).

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