Programmable integer and fractional frequency divider

Details Programmable integer and fractional frequency divider Programmable integer and fractional frequency divider

2007-12-29

2009-06-23

Lam, Tuan (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

07551707

ABSTRACT:
A programmable integer and fractional frequency divider is provided. The programmable divider divides a frequency of an input signal by a first divisor to generate an output signal, and comprises a programmable integer frequency divider and a fractional number switch. The programmable integer frequency divider divides the frequency of the input signal by a second divisor to generate the output signal, wherein the second divisor is first or second integers depending on a divisor switching signal. The fractional number switch calculates a pulse count of the output signal, and generates the divisor switching signal to switch from the first to the second integer when the pulse count of the output signal equals to a predetermined pulse count determined by a fractional part of the first divisor, and receives a fractional divisor control signal to change the predetermined pulse count, thereby changing the fractional part of the first divisor.

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Michael H. Perrott et al., “A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation”, IEEE Journal of Solid-State Circuits, Dec. 1997, pp. 2048-2060, vol. 32, No. 12, IEEE, US.
Jan Craninckx et al., “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer”, IEEE Journal of Solid-State Circuits, Dec. 1998, pp. 2054-2065, vol. 33, No. 12, IEEE, US.

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