Methods, apparatus, and systems for flash memory bit line...

Details Methods, apparatus, and systems for flash memory bit line... Methods, apparatus, and systems for flash memory bit line...

2006-12-28

2009-02-03

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185120, C365S185180

Reexamination Certificate

active

07486566

ABSTRACT:
Various embodiments include a circuit to receive data information, a memory array including memory cells coupled to a bit line, and control circuitry to charge the bit line while the data information is received at the circuit. The control circuitry may program the data information into a selected memory cell of the memory cells after the data information is received at the circuit. Other embodiments including additional methods, apparatus, and systems are disclosed.

REFERENCES:
patent: 6813187 (2004-11-01), Lee
patent: 6879520 (2005-04-01), Hosono et al.
patent: 2008/0005416 (2008-01-01), Telecco

Affiliated with

Also associated with

Rating

Methods, apparatus, and systems for flash memory bit line... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods, apparatus, and systems for flash memory bit line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods, apparatus, and systems for flash memory bit line... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4059463