Method to improve testing speed of memory

Details Method to improve testing speed of memory Method to improve testing speed of memory

1997-12-17

1999-05-25

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

059075619

ABSTRACT:
A method of testing a semiconductor memory device using a parallel march pattern method of testing. All of the memory bits in a memory device are programmed to a first logic state. All of the memory bits in selected rows are programmed to a second logic state. All of the memory bits in rows adjacent to the rows programmed to the second logic state are read to determine if the memory bits programmed to the second logic state have caused the memory bits programmed to the first logic state in the adjacent rows to change logic state. The selected rows are determined by a periodicity value that can be values such as 4, 8, or 16. The periodicity determines the number of clock cycles needed to test the entire memory device. A periodicity of 8 requires only 8 clock cycles to test the entire memory device, regardless of the size of the memory device. The parallel march pattern method of testing can be by rows, by columns or by diagonals.

REFERENCES:
patent: 5706234 (1998-01-01), JPilch, Jr. et al.

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