Method of reducing process steps in metal line protective...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S739000, C257S758000, C257S762000, C257S773000, C257S774000, C257S776000, C257SE23020, C257SE23173, C257SE23174

Reexamination Certificate

active

07495335

ABSTRACT:
A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal line and forming a protective plate in the plate opening on the top metal line.

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patent: 5894170 (1999-04-01), Ishikawa
patent: 6265300 (2001-07-01), Bhansali et al.
patent: 6897570 (2005-05-01), Nakajima et al.
patent: 2001/0008311 (2001-07-01), Harada et al.

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