Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-05-25
2009-06-09
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S078000, C365S189020, C365S189050, C365S189110, C365S220000, C365S221000, C711S117000, C711S104000, C257S700000, C257S777000, C257S686000
Reexamination Certificate
active
07545663
ABSTRACT:
Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.
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Chinese Office Action, with English Translation, issued in Chinese Patent Application No. CN 2006100899003 dated on Dec. 12, 2008.
Ikeda Hiroaki
Iwata Atsushi
Sasaki Mamoru
Elpida Memory Inc.
Hidalgo Fernando N
Ho Hoai V
McDermott Will & Emery LLP
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