Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-01-20
1999-05-25
Mai, Son
Static information storage and retrieval
Floating gate
Particular biasing
36518518, 36518527, G11C 1604
Patent
active
059075066
ABSTRACT:
In non-volatile semiconductor memory erasing method and device, in an erasing operation, a negative potential is applied to the gate of each memory cell (MC00 to MCmn), a positive potential which is equal or above a supply voltage Vcc from the external is applied to the channel of each memory cell, and the source and drain of each memory cell are connected to the ground potential through a high-resistant current path by a cell voltage control circuit, thereby obtaining a stable erasing characteristic in the erasing operation.
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Toshikatsu Jinbo et al., IEEE Journal of Solid State Circuits, vol. 27, No. 11, A 5-V-Only 16-Mb Flash Memory with Sector Erase Mode, Nov. 1992, pp. 1547-1554.
Albert Bergemont et al., IEEE Transactions on Electron Devices, vol. 43, No. 9, Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications, Sep. 1992, pp. 1510-1517.
Mai Son
NEC Corporation
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