1978-12-27
1981-08-18
Wojciechowicz, Edward J.
357 41, 357 55, H01L 2980
Patent
active
042849993
ABSTRACT:
An integrated semiconductor junction field effect transistor logic device has a semiconductor substrate of one conductivity type having a high impurity concentration and a relatively low impurity concentration epitaxial semiconductor layer of the same conductivity type formed on the substrate and constituting a channel region. Two parallel grooves are formed in a surface portion of the epitaxial layer with a ridge between them. A drain region of the same conductivity type as the substrate is formed the ridge between the two grooves while a gate region of opposite conductivity type has a portion under one groove and a portion under and along the outer side of the other groove. A drain electrode is provided on the ridge between the two grooves and a gate electrode is provided on the gate region along the outer side of one groove. Since the gate-drain capacity is reduced, the semiconductor device can operate at high speed.
REFERENCES:
patent: 4156879 (1979-05-01), Lee
patent: 4167745 (1979-09-01), Ishibashi
patent: 4198648 (1980-04-01), Nishizawa
Adams Bruce L.
Burns Robert E.
Kabushiki Kaisha Daini Seikosha
Lobato Emmanuel J.
Wojciechowicz Edward J.
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