Method of fabricating non-volatile semiconductor memory device

Details Method of fabricating non-volatile semiconductor memory device Method of fabricating non-volatile semiconductor memory device

1993-10-27

1995-09-12

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 44, H01L 218247

Patent

active

054496349

ABSTRACT:
An MOS transistor having an LDD structure is constructed in a first active region for a peripheral circuit in alignment with a first gate, by using as a mask a second active region for a memory cell. After forming a first interlayer insulating layer, a second gate having a floating gate and a control gate is formed in the second active region. A third insulating layer formed on the surface including the second gate is patterned to form a contact hole bounded by a sidewall of a side face of the second gate.

REFERENCES:
patent: 4373249 (1983-02-01), Kosa et al.
patent: 4775642 (1988-10-01), Chang et al.
patent: 5175120 (1992-12-01), Lee
Patent Abstracts of Japan, vol. 8, No. 21 (E-224), Jan. 28, 1984.
Patent Abstracts of Japan, vol. 14, No. 463 (E-0988), Oct. 8, 1990.

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