Method for manufacturing integrated circuit

Details Method for manufacturing integrated circuit Method for manufacturing integrated circuit

2007-04-24

2008-12-09

Clark, S. V (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S022000, C438S042000, C438S043000

Reexamination Certificate

active

07462567

ABSTRACT:
The flatness of the surface of the light-receiving portion must be increased when the upper structural layer of a light detector is etched. The present invention provides a method for manufacturing an integrated circuit in which an aperture is formed in a stack in which an underlayer, a light-receiving area pad, and an upper structural layer are layered on a substrate, the method comprising a light-receiving area pad etching step for etching the structural layer and the light-receiving area pad under etching conditions in which a high selectivity ratio is maintained between the upper structural layer and the light-receiving area pad; and an underlayer etching step for switching to etching conditions in which the light-receiving area pad has a high selectivity ratio in relation to the underlayer following the light-receiving area pad etching step, and etching the light-receiving area pad and the underlayer. The bottom surface of the aperture can thereby be made flatter and the amount of incident light in the plane of the light-receiving portion can be made more uniform.

REFERENCES:
patent: 6873025 (2005-03-01), Wada et al.
patent: 2002/0110950 (2002-08-01), Matsuda
patent: 2003/0228084 (2003-12-01), Kanda et al.
patent: 2005/0205997 (2005-09-01), Yamamoto et al.
patent: 2006/0154034 (2006-07-01), Araki
patent: 2007/0018263 (2007-01-01), Noma

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