Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2004-10-07
2008-12-16
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185110
Reexamination Certificate
active
07466588
ABSTRACT:
A high voltage up to 20V is usually applied to a NAND flash memory device for programming or easing a memory section. The programming/easing voltage must reach that high voltage state when the R/B signal is in the L state to start the actual cell programming or erasing. To improve the programming or erasing efficiency, the applied voltage also reaches the high voltage state before the R/B signal is set from H to L. The memory device may have one connecting pad to receive a normal operating voltage and another connection pad to receive the programming and erasing voltage. The EXT_CSD register may have a mode bit to indicate whether the memory device supports the programming and erasing operation.
REFERENCES:
patent: 5414829 (1995-05-01), Fandrich et al.
patent: 6128231 (2000-10-01), Chung
patent: 6256229 (2001-07-01), Roohparvar
patent: 6288936 (2001-09-01), Kawamura
patent: 6335881 (2002-01-01), Kim et al.
patent: 6552933 (2003-04-01), Roohparvar
patent: 6781881 (2004-08-01), Chih
patent: 7031190 (2006-04-01), Lee
patent: 2003/0058692 (2003-03-01), Shiga
patent: 2004/0167653 (2004-08-01), Kaki et al.
patent: WO 98/29890 (1998-07-01), None
Hoang Huan
Nokia Corporation
Ware Fressola Van Der Sluys & Adolphson LLP
LandOfFree
Method for improving programming speed in memory devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving programming speed in memory devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving programming speed in memory devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4048730