Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2006-10-20
2008-11-11
Nguyen, Khai M (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000, C341S172000, C327S157000
Reexamination Certificate
active
07450048
ABSTRACT:
An error reducing comparator based switch capacitor (CBSC) circuit comprises: a comparator of a substantial offset, a charge pump controlled by an output of the comparator, and a plurality of capacitors. The CBSC circuit cyclically operates through a sampling phase, and a transfer phase. During the sampling phase, an input voltage is sampled by a first capacitor. During the transfer phase, the charge stored on the first capacitor is transferred to a second capacitor through injecting or draining charge using the charge pump. The amount of the offset is properly set to reduce an error due to circuit delay of the CBSC circuit.
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Hsu Winston
Nguyen Khai M
Realtek Semiconductor Corp.
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