Integrated circuit structures for increasing resistance to...

Details Integrated circuit structures for increasing resistance to... Integrated circuit structures for increasing resistance to...

2007-12-05

2008-12-16

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular chip input/output means

C257S202000, C257S298000

Reexamination Certificate

active

07465971

ABSTRACT:
A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

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