Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2004-12-21
2008-12-16
Malzahn, David H (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07467175
ABSTRACT:
Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.
REFERENCES:
patent: 4639888 (1987-01-01), Nussbaecher
patent: 4680628 (1987-07-01), Wojcik et al.
patent: 4780842 (1988-10-01), Morton et al.
patent: 5095523 (1992-03-01), Delaruelle et al.
patent: 5317530 (1994-05-01), Toriumi
patent: 5339264 (1994-08-01), Said et al.
patent: 5349250 (1994-09-01), New
patent: 5388062 (1995-02-01), Knutson
patent: 5450339 (1995-09-01), Chester et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5506799 (1996-04-01), Nakao
patent: 5572207 (1996-11-01), Harding et al.
patent: 5600265 (1997-02-01), El Gamal et al.
patent: 5642382 (1997-06-01), Juan
patent: 5724276 (1998-03-01), Rose et al.
patent: 5732004 (1998-03-01), Brown
patent: 5754459 (1998-05-01), Telikepalli
patent: 5809292 (1998-09-01), Wilkinson et al.
patent: 5828229 (1998-10-01), Cliff et al.
patent: 5838165 (1998-11-01), Chatter
patent: 5883525 (1999-03-01), Tavana et al.
patent: 5914616 (1999-06-01), Young et al.
patent: 5933023 (1999-08-01), Young
patent: 6000835 (1999-12-01), Pan et al.
patent: 6014684 (2000-01-01), Hoffman
patent: 6038583 (2000-03-01), Oberman et al.
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6100715 (2000-08-01), Agrawal et al.
patent: 6108343 (2000-08-01), Cruickshank et al.
patent: 6131105 (2000-10-01), Pajarre et al.
patent: 6134574 (2000-10-01), Oberman et al.
patent: 6154049 (2000-11-01), New
patent: 6204689 (2001-03-01), Percey et al.
patent: 6223198 (2001-04-01), Oberman et al.
patent: 6243808 (2001-06-01), Wang
patent: 6249144 (2001-06-01), Agrawal et al.
patent: 6260053 (2001-07-01), Maulik et al.
patent: 6269384 (2001-07-01), Oberman
patent: 6282627 (2001-08-01), Wong et al.
patent: 6282631 (2001-08-01), Arbel
patent: 6288566 (2001-09-01), Hanrahan et al.
patent: 6298366 (2001-10-01), Gatherer et al.
patent: 6298472 (2001-10-01), Phillips et al.
patent: 6311200 (2001-10-01), Hanrahan et al.
patent: 6323680 (2001-11-01), Pedersen et al.
patent: 6341318 (2002-01-01), Dakhil
patent: 6347346 (2002-02-01), Taylor
patent: 6349346 (2002-02-01), Hanrahan et al.
patent: 6362650 (2002-03-01), New et al.
patent: 6366943 (2002-04-01), Clinton
patent: 6370596 (2002-04-01), Dakhil
patent: 6374312 (2002-04-01), Pearce et al.
patent: 6385751 (2002-05-01), Wolf
patent: 6389579 (2002-05-01), Phillips et al.
patent: 6392912 (2002-05-01), Hanrahan et al.
patent: 6397238 (2002-05-01), Oberman et al.
patent: 6438570 (2002-08-01), Miller
patent: 6448808 (2002-09-01), Young et al.
patent: 6449708 (2002-09-01), Dewhurst et al.
patent: 6457116 (2002-09-01), Mirsky et al.
patent: 6483343 (2002-11-01), Faith et al.
patent: 6496918 (2002-12-01), DeHon et al.
patent: 6519674 (2003-02-01), Lam et al.
patent: 6526430 (2003-02-01), Hung et al.
patent: 6526557 (2003-02-01), Young et al.
patent: 6530010 (2003-03-01), Hung et al.
patent: 6538470 (2003-03-01), Langhammer et al.
patent: 6539477 (2003-03-01), Seawright
patent: 6556044 (2003-04-01), Langhammer et al.
patent: 6573749 (2003-06-01), New et al.
patent: 6693455 (2004-02-01), Langhammer et al.
patent: 6820102 (2004-11-01), Aldrich et al.
patent: 6864714 (2005-03-01), Digari et al.
patent: 6873182 (2005-03-01), Mohan et al.
patent: 6904446 (2005-06-01), Dibrino
patent: 6920627 (2005-07-01), Blodget et al.
patent: 6925480 (2005-08-01), Duborgel
patent: 6947916 (2005-09-01), Luo et al.
patent: 7129762 (2006-10-01), Vadi
patent: 7142010 (2006-11-01), Langhammer et al.
patent: 7174432 (2007-02-01), Howard et al.
patent: 7178130 (2007-02-01), Chuang et al.
patent: 7193433 (2007-03-01), Young
patent: 7194598 (2007-03-01), Jacob
patent: 7197686 (2007-03-01), Box et al.
patent: 2002/0138538 (2002-09-01), Talwar et al.
patent: 2002/0138716 (2002-09-01), Master et al.
patent: 2003/0041082 (2003-02-01), Dibrino
patent: 2003/0055861 (2003-03-01), Lai et al.
patent: 2003/0105949 (2003-06-01), Master et al.
patent: 2003/0140077 (2003-07-01), Zaboronski et al.
patent: 2003/0154357 (2003-08-01), Master et al.
patent: 2004/0010645 (2004-01-01), Scheuermann
patent: 2004/0030736 (2004-02-01), Scheuermann
patent: 2004/0078403 (2004-04-01), Scheuermann et al.
patent: 2004/0093465 (2004-05-01), Ramchandran
patent: 2004/0093479 (2004-05-01), Ramchandran
patent: 2004/0143724 (2004-07-01), Jacob et al.
patent: 2004/0168044 (2004-08-01), Ramchandran
patent: 2004/0181614 (2004-09-01), Furtek et al.
patent: 2005/0038984 (2005-02-01), Heidari-Bateni et al.
patent: 2005/0039185 (2005-02-01), Heidari-Bateni et al.
patent: 2005/0144210 (2005-06-01), Simkins et al.
patent: 2005/0144211 (2005-06-01), Simkins et al.
patent: 2005/0144212 (2005-06-01), Simkins et al.
patent: 2005/0144213 (2005-06-01), Simkins et al.
patent: 2005/0144216 (2005-06-01), Simkins et al.
patent: 2005/0187998 (2005-08-01), Zheng et al.
patent: 2006/0015701 (2006-01-01), Hogenauer
patent: 2006/0190516 (2006-08-01), Simkins et al.
patent: 2006/0190518 (2006-08-01), Ekner et al.
patent: 2006/0195496 (2006-08-01), Vadi et al.
patent: 2006/0206557 (2006-09-01), Wong et al.
patent: 2006/0212499 (2006-09-01), New et al.
patent: 2006/0230092 (2006-10-01), Ching et al.
patent: 2006/0230093 (2006-10-01), New et al.
patent: 2006/0230094 (2006-10-01), Simkins et al.
patent: 2006/0230095 (2006-10-01), Simkins et al.
patent: 2006/0230096 (2006-10-01), Thendean et al.
patent: 2006/0288069 (2006-12-01), Simkins et al.
patent: 2006/0288070 (2006-12-01), Vadi et al.
patent: 2 365 636 (2002-02-01), None
patent: 2 373 883 (2002-10-01), None
patent: 2 383 435 (2003-06-01), None
patent: WO 01/89091 (2001-11-01), None
patent: WO 2005/066832 (2005-07-01), None
patent: WO 2005/010049 (2005-11-01), None
patent: WO 2005/110049 (2005-11-01), None
U.S. Appl. No. 11/019,518, filed Dec. 21, 2004, Simkins, James M. et al., Applications of Cascading DSP Slices, Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124.
Fijioka, Y. et al., “Design of a Reconfigurable Parallel Processor for Digital control Using FPGAs”, IEICE Transactions on Electronics, Institute of Electronics Information and communications, vol. E77-C, No. 7; Jul. 1994; pp. 1123-1129.
Xilinx, Inc., “The Programmable Logic Data Book 1999,” pp. 1-62, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx, Inc., “Virtex4 FPGA Handbook” Ch. 10 ExtremeDSP Design Considerations, Aug. 2, 2004, pp. 461-508, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Altera; “Using PLDs for High-Performance DSP Applications”; White Paper, WP-STXDSP-1.0; Feb. 2002, Ver. 1.0; Preliminary Information; pp. 1-6.
Leitung: Prof. Dr. Miroslaw Malek; Humbolt-Universitat Zu Berlin, Institut for Informatik; Lecture 12; “ALU (3)—Division Algorithms”; Sommersemester 2002; available from www.informatik.hu-berlin.ed/tok/ca; pp. 1-15.
Xilinx, Inc.; “FPGAs and DSP”; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 1-8.
Gary Harmon; “Silicon Arithmetic with a 40% Advantage”; White Paper; AutoPD; pp. 1-3.
Herma Dhanesha et al.; “Array-of-arrays Architecture for Parallel Floating Point Multiplication”; Center for Integrated Systems, Stanford University, Stanford, CA; p
Ching Alvin Y.
New Bernard J.
Simkins James M.
Wong Jennifer
Young Steven P.
Behiel Arthur J.
Malzahn David H
Webostad W. Eric
XILINX Inc.
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