Negative wordline bias for reduction of leakage current...

Details Negative wordline bias for reduction of leakage current... Negative wordline bias for reduction of leakage current...

2006-12-22

2008-12-09

Mai, Son L (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220

Reexamination Certificate

active

07463525

ABSTRACT:
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.

REFERENCES:
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patent: 6301155 (2001-10-01), Fujiwara
patent: 7075143 (2006-07-01), Fujiwara et al.
patent: 7319616 (2008-01-01), Sundaram et al.
patent: 2006/0039195 (2006-02-01), Kurata et al.

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