Microprocessor which optimizes bus utilization based upon bus sp

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395375, 364DIG1, 3642405, 3642624, 3642631, 3642719, G06F 928

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053296214

ABSTRACT:
A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.

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Branch Folding in the CRISP Microprocessor: Reducing Brach Delay to Zero, by David R. Ditzel and Hubert R. McLellan, 1987 ACM0084-7495/87/06000, pp. 2-9.
An Evaluation of Brach Architectures, by John A. DeRosa and Henry M. Levy, 1987 ACM 0084-7495/87/0600, pp. 10-16.

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