Device having reduced chemical mechanical planarization

Details Device having reduced chemical mechanical planarization Device having reduced chemical mechanical planarization

Filed on

2006-06-27

Date issued

2008-11-18

Examiner

Parekh, Nitin (Department: 2811)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Combined with electrical contact or lead

SubSubClass

Of specified configuration

Other Related Categories

C257S758000, C257SE21583, C438S633000

Type

Reexamination Certificate

Status

active

Patent number

07453152

Description

ABSTRACT:
The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a semiconductor wafer to reduce the amount of material removed during chemical mechanical planarization (CMP) of the metal layer. This hardened layer may be produced, for example, by oxidizing the metal surface and/or coating the metal surface with a polymer. In one implementation, a relatively thick and dense oxide layer is formed on the wafer metal surface prior to CMP, by injecting, for example, an oxidant, such as oxygen or ozone, near the end of an annealing cycle. The hardened metal beneficially protects recessed regions from CMP chemical attack and CMP pad deformation, and thus reduces the thickness-to-planarity, dishing, and waste generation realized during CMP.

REFERENCES:
patent: 5552638 (1996-09-01), O'Connor et al.
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6649523 (2003-11-01), Basol et al.
patent: 6702954 (2004-03-01), Her et al.
patent: 2003/0020141 (2003-01-01), Thomas
patent: 2005/0074967 (2005-04-01), Kondo et al.
patent: 2005/0085066 (2005-04-01), Tsao et al.

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