Memory having parity error correction

Details Memory having parity error correction Memory having parity error correction

2005-10-26

2008-12-30

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185070, C365S189050, C365S230080, C365S233100

Reexamination Certificate

active

07471569

ABSTRACT:
A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

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U.S. Appl. No. 11/153,795, filed Jun. 2005, Hummler, Klaus.

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