Non-volatile memory device and method of programming a multi...

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185210, C365S185250

Reexamination Certificate

active

07466587

ABSTRACT:
A non-volatile memory device of the present invention includes a page buffer having a bit line selecting circuit, a first register, a second register, a data comparing circuit, a first bit line voltage controller, and a second bit line voltage controller. The bit line selecting circuit couples selectively a certain bit line to a sensing node. The first register and the second register store given data. The data comparing circuit compares the data stored in the first register with the data stored in the second register, and transmits the comparison result to the sensing node. The first bit line voltage controller applies a voltage of low level to the bit line in accordance with a voltage level of the data stored in the first register. The second bit line voltage controller applies a selected first voltage of high level to the bit line in accordance with the data stored in the second register.

REFERENCES:
patent: 7336532 (2008-02-01), Chen
patent: 7366014 (2008-04-01), Micheloni et al.
patent: 1020060052142 (2006-05-01), None
patent: 1020060056236 (2006-05-01), None
patent: 1020060067579 (2006-06-01), None
patent: 1020060068969 (2006-06-01), None
patent: 1020060070734 (2006-06-01), None

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