Self-aligned and process-adjusted high density power transistor

Details Self-aligned and process-adjusted high density power transistor Self-aligned and process-adjusted high density power transistor

1997-04-18

1999-05-25

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257286, 257328, 257335, H01L 2976

Patent

active

059071699

ABSTRACT:
The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary. The MOSFET transistor further includes a thin gate oxide layer overlying the top surface of the substrate and an edge of the raised oxide terrace. The MOSFET transistor further includes a polysilicon gate overlaying the oxide block and the silicon terrace, the gate further covering an area above the source region and the body region insulated by the gate oxide layer therefrom.

REFERENCES:
patent: 4960723 (1990-10-01), Davies
patent: 5273922 (1993-12-01), Tsoi
patent: 5504360 (1996-04-01), Tokura et al.
patent: 5563437 (1996-10-01), Davies et al.

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