Single deposition layer metal dynamic random access memory

Details Single deposition layer metal dynamic random access memory Single deposition layer metal dynamic random access memory

1997-05-08

1999-05-25

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

257203, 257207, 257666, H01L 310328, H01L 310336, H01L 31072

Patent

active

059071664

ABSTRACT:
A 16 megabit (2.sup.24) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

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