Memory row decoder

Details Memory row decoder Memory row decoder

2006-10-26

2008-11-04

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189090

Reexamination Certificate

active

07447105

ABSTRACT:
A memory row decoder is disclosed, comprising a first depletion NMOS transistor having a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal, a first enhancement PMOS transistor having a second source/drain coupled to the second partially decoded signal, and a gate coupled to a first source/drain of the first depletion NMOS transistor, a first enhancement NMOS transistor having a first source/drain coupled to a first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to a first reference potential, and a gate coupled to the first partially decoded signal, and a second enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to the first reference potential, and a gate coupled to a reset signal. The first enhancement PMOS transistor has reduced GIDL current and thus the memory row decoder consumes less power in an unselected mode.

REFERENCES:
patent: 5365479 (1994-11-01), Hoang et al.
patent: 5563842 (1996-10-01), Challa
patent: 5636175 (1997-06-01), McLaury
patent: 7277315 (2007-10-01), Yuan et al.

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