PMOS three-terminal non-volatile memory element and method...

Details PMOS three-terminal non-volatile memory element and method... PMOS three-terminal non-volatile memory element and method...

Filed on

2005-08-24

Date issued

2008-11-11

Examiner

Le, Thong Q. (Department: 2827)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular biasing

Other Related Categories

C365S185140, C365S208000

Type

Reexamination Certificate

Status

active

Patent number

07450431

Description

ABSTRACT:
A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

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