Digital data arbitration apparatus

Details Digital data arbitration apparatus Digital data arbitration apparatus

1993-04-02

1994-07-12

Safourek, Benedict V.

Multiplex communications

Wide area network

Packet switching

370112, 307243, H04J 302

Patent

active

053295293

ABSTRACT:
A data arbitration apparatus for combining data from a plurality of data paths, wherein data from the respective data paths are clocked by respective clock signals asynchronously and at different rates includes a multiplexer to which the respective data paths are coupled. The output of the multiplexer is applied to a "D"-type register having a dock input terminal coupled to one of the respective clock signals. The D-type register provides the combined data signal. A logic arrangement is coupled to the respective clock signals for providing control signals according to a hierarchy of importance of the signals occurring on the respective data paths. The control signals are coupled to condition the multiplexer to provide data samples from the respective data paths according to the established hierarchy. The logic arrangement is constructed such that the multiplexer switches to a different data path on a predetermined transition of the clock signal for that data path and switches back to the prior connected data path on the next predetermined transition of the clock signal associated with such prior connected data path.

REFERENCES:
patent: 3781818 (1973-12-01), Pardoe et al.
patent: 3838296 (1974-09-01), McLeod
patent: 5111455 (1992-05-01), Neaus

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