Electrostatic discharge protection circuit and semiconductor...

Details Electrostatic discharge protection circuit and semiconductor... Electrostatic discharge protection circuit and semiconductor...

2005-06-03

2008-11-11

Sherry, Michael J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S093100, C361S111000, C361S118000

Reexamination Certificate

active

07450357

ABSTRACT:
An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting an ESD current and a bypass circuit for bypassing the ESD current is provided. The detection circuit and the bypass circuit are coupled between a first pad and a second pad. The bypass circuit comprises a transistor, a diode, and a resistor. The drain of the transistor is coupled to the first pad. The source of the transistor is coupled to the second pad and a cathode of the diode. The substrate terminal of the transistor is coupled to an anode of the diode and an output terminal of the detection circuit. The resistor is coupled between the substrate terminal and the second pad. The diode keeps the voltage of the substrate terminal sufficient for turning on the transistor.

REFERENCES:
patent: 6034397 (2000-03-01), Voldman
patent: 6465768 (2002-10-01), Ker et al.
patent: 6628159 (2003-09-01), Voldman
patent: 6747501 (2004-06-01), Ker et al.
patent: 2004/0212936 (2004-10-01), Salling et al.
patent: 2005/0047036 (2005-03-01), Liu et al.
patent: 2006/0050451 (2006-03-01), Jen-Chou
Article titled “A Fail-Safe ESD Protection Circuit with 230 fF Linear Capacitance for High-Speed/High-Precision 0.18 μm CMOS I/O Application” jointly published by Lin et al. in 2002. (4 pages).
Article titled “Substrate Pump NMOS for ESD Protection Applications” jointly published by Duvvury et al. in 2002. (11 pages).

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