Operating method of non-volatile memory device

Details Operating method of non-volatile memory device Operating method of non-volatile memory device

2006-10-30

2008-12-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280

Reexamination Certificate

active

07463530

ABSTRACT:
An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.

REFERENCES:
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5587947 (1996-12-01), Chang et al.
patent: 5940325 (1999-08-01), Chang et al.
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6011725 (2000-01-01), Eitan et al.
patent: 6026026 (2000-02-01), Chan et al.
patent: 6074917 (2000-06-01), Chang et al.
patent: 6169693 (2001-01-01), Chan et al.
patent: 6218700 (2001-04-01), Papadas et al.
patent: 6512696 (2003-01-01), Fan et al.
patent: 6709928 (2004-03-01), Jenne et al.
patent: 6720630 (2004-04-01), Mandelman et al.
patent: 6744675 (2004-06-01), Zheng et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6818558 (2004-11-01), Rathor et al.
patent: 6897533 (2005-05-01), Yang et al.
patent: 6912163 (2005-06-01), Zheng et al.
patent: 7075828 (2006-07-01), Lue et al.
patent: 7115469 (2006-10-01), Halliyal et al.
patent: 7115942 (2006-10-01), Wang
patent: 7133313 (2006-11-01), Shih et al.
patent: 7151692 (2006-12-01), Wu et al.
patent: 7164603 (2007-01-01), Shih et al.
patent: 7190614 (2007-03-01), Wu et al.
patent: 7209390 (2007-04-01), Lue et al.
patent: 7394702 (2008-07-01), Ding et al.
patent: 2003/0030100 (2003-02-01), Lee et al.
patent: 2003/0032242 (2003-02-01), Lee et al.
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0146465 (2003-08-01), Wu
patent: 2003/0224564 (2003-12-01), Kang et al.
patent: 2004/0079983 (2004-04-01), Chae et al.
patent: 2004/0183126 (2004-09-01), Bae et al.
patent: 2005/0006696 (2005-01-01), Noguchi et al.
patent: 2005/0023603 (2005-02-01), Eldridge et al.
patent: 2005/0074937 (2005-04-01), Jung
patent: 2005/0093054 (2005-05-01), Jung
patent: 2005/0219906 (2005-10-01), Wu
patent: 2005/0237801 (2005-10-01), Shih
patent: 2005/0237809 (2005-10-01), Shih et al.
patent: 2005/0237813 (2005-10-01), Zous et al.
patent: 2005/0237815 (2005-10-01), Lue et al.
patent: 2005/0237816 (2005-10-01), Lue et al.
patent: 2005/0270849 (2005-12-01), Lue
patent: 2005/0281085 (2005-12-01), Wu
patent: 2006/0198189 (2006-09-01), Lue et al.
patent: 2006/0198190 (2006-09-01), Lue
patent: 2006/0202252 (2006-09-01), Wang et al.
patent: 2006/0202261 (2006-09-01), Lue et al.
patent: 2006/0258090 (2006-11-01), Bhattacharyya et al.
patent: 2006/0261401 (2006-11-01), Bhattacharyya
patent: 2006/0281260 (2006-12-01), Lue
patent: 2007/0012988 (2007-01-01), Bhattacharyya
patent: 2007/0029625 (2007-02-01), Lue et al.
patent: 2007/0031999 (2007-02-01), Ho et al.
patent: 2007/0045718 (2007-03-01), Bhattacharyya
patent: 2007/0069283 (2007-03-01), Shih et al.
patent: 0016246 (1980-10-01), None
patent: 1411555 (2004-04-01), None
patent: 2004363329 (2004-12-01), None
White et al., “On the Go with SONOS” IEEE Circuits and Devices, Jul. 2000, 22-31.
Walker, et al., “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications,” 2003 Symposium on VLSI Tech Digest of Technical Papers, 29-30.
Minami et al., “New Scaling Guidelines for MNOS Nonvolatile Memory Devices,” IEEE Trans on Electron Devices 38(11) Nov. 1991 2519-2526.
Ito et al., “A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications,” 2004 Symp. on VLSI Tech Digest of Tech Papers 2004, 80-81.
Eitan et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett 21(11) Nov. 2000, 543-545.
Chindalore et al., “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE Electron Dev Lett 24(4) Apr. 2003, 257-259.
Dimaria, D.J., et al., “Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents,” IBM J. Res. Dev. May 1977, 227-244.
Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEDM Tech Digest 2002, 931-934.
Hijaya, S., et al., “High-Speed Write/Erase EAROM Cell with Graded Energy BAnd-Gap Insulator,” Electronics and Comm in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36.
Hinkle, C.L., et al., “Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 Layers,” Surface Science Sep. 20, 2004, vol. 566-568, 1185-1189.
Buckley, J., et al., “Engineering of ‘Conduction band—Crested Barriers’ or ‘Dielectric Constant—Crested Barriers’ in view of their application of floating-gate non-volatile memory devices,” VLSI 2004, 55-56.
Takata, M., et al., “New Non-Volatile Memory with Extremely High Density Metal Nano-Dots,” IEEE IEDM 03-553, 22.5.1-22.5.4.
Lee, Chungho, et al., “Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals,” IEEE IEDM 03-557, 22.6.1-22.6.4.
Baik, Seung, et al., “High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier,” IEEE IEDM 03-545, 22.3.1-22.3.4.
Lee, Chang, et al., “A Novel SONOS Structure of SiO2/SiN/AI2O3 with TaN Metal Gate for Multi-Giga Bit Flash Memeries,” IEEE 2003, 4 pages.
Cho et al., “Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells,” IEEE Electron Device Lett., vol. 24, No. 4, Apr. 2003, 260-262.
Shih et al., “A Novel 2-bit/cell Nitride Storage Flash memory with Greater than 1M P/E-cycle Endurance,” IEEE IEDM 2004, pp. 36.3.1-36.3.4.
Blomme, et al., “Multilayer tunneling barriers for nonvolatile memory applications,” 60th Device Resarch Conf., 2002, Conf. Digest 153-154.
Blomme, et al., Write/Erase Cycling Endurance of Memory Cells with SiO2/HfO2 Tunnel Dielectric, IEEE Trans on Device and Materials Reliability, vol. 4, No. 3, Sep. 2004, 345-351.
Govoreanu, et al, “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,” IEEE Electron Device Lett., vol. 24, No. 2, Feb. 2003, 99-101.
Govoreanu et al., “Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics,” IEEE SISPAD Int'l Conf. 305 Sep. 2003, 299-302.
Govoreanu et al., “An Investigation of the Electron Tunneling Leakage Current through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions,” IEEE SISPAD Int'l Conf. Sep. 3-5, 2003, 287-290.
Kim et al., “Robust Multi-bit Programmable Flash Memory Using a Resonant Tunnel Barrier,” Electron Dev. Mtg. Dec. 5-7, 2005, IEDM Tech Dig. 861-864.
Likharev, “Layered tunnel barriers for nonvolatile memory devices,” Applied Physics Lett, vol. 73, No. 15, Oct. 1998, 2137-2139.
Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability,” IEDM Tech Digest, IEEE Int'l Dec. 2005, 547-550.
Sune, et al., “Multi-layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time,” IEEE 2002 Nanoelectronics Workshop, Jun. 2002, 83-84.
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