Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2004-09-08
2008-08-19
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S225000, C712S216000
Reexamination Certificate
active
07415597
ABSTRACT:
A processor may include a scheduler configured to issue operations and a load store unit configured to execute memory operations issued by the scheduler. The load store unit is configured to store information identifying memory operations issued to the load store unit. In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit is configured to replay at least one of the issued memory operations by providing an indication to the scheduler. The scheduler is configured to responsively reissue the memory operations identified by the load store unit.
REFERENCES:
patent: 5615350 (1997-03-01), Hesson et al.
patent: 5781752 (1998-07-01), Moshovos et al.
patent: 6415380 (2002-07-01), Sato
patent: 6502188 (2002-12-01), Zuraski et al.
patent: 6542984 (2003-04-01), Keller et al.
patent: 6658554 (2003-12-01), Moshovos et al.
patent: 6950925 (2005-09-01), Sander et al.
patent: 6970997 (2005-11-01), Shibayama et al.
patent: 2003/0088760 (2003-05-01), Chowdhury et al.
patent: 2003/0236969 (2003-12-01), Kacevas et al.
patent: 2004/0143721 (2004-07-01), Pickett et al.
patent: 2004/0177236 (2004-09-01), Pickett
patent: 2004/0255101 (2004-12-01), Filippo et al.
patent: WO 03/093982 (2003-11-01), None
patent: WO 2004/021173 (2004-03-01), None
Authors Mikko H. Lipasti; Christopher B. Wilkerson; John Paul Shen “Value locality and load value prediction” Publisher: ACM Press Year of Publication: 1996.
Moshovos, A.; Sohi, G.S.; “Memory dependence speculation tradeoffs in centralized, continuous-window superscalar processors”, IEEE, Pertinent pp. 1-12, Year of publication: Jan. 8, 2000.
Black et al. “Load Execution Latency Reduction”, ACM. Pertinent pp. 29-36; Year of publication: Jul. 12, 1998.
International Search Report for PCT/US2005/022426, mailed Apr. 10, 2006.
International Search Report and Written Opinion for PCT/US2005/022426, mailed Jun. 8, 2006.
Reinman, et al., “Predictive Techniques for Aggressive Load Speculation,” ACM/IEEE International Symposium on Microarchitecture, 1998, pp. 127-137.
Reinman, et al., “Predictive Techniques for Aggressive Load Speculation,” ACM/IEEE International Symposium on Microarchitecture, 1998, pp. 127-137, Nov. 30, 1998.
Andreas Moshovos, et al., “Memory Dependence Prediction in Multimedia Applications,” 18 pages, May 2000.
Stephan Jourdan, et al., “A Novel Renaming Scheme to Exploit Value Temporal Locality through Physical Register Reuse and Unification,” Intel Corporation, IEEE, 1998, 10 pages, Dec. 1998.
Soner Onder, et al., “Load and Store Reuse Using Register File Contents,” ACM 15thInternational Conference on Supercomputing, Sorrento, Naples, Italy, Jun. 2001, pp. 289-302, Jun. 2001.
Michael Bekerman, et al., “Early Load Address Resolution Via Register Tracking,” Intel Corporation, 9 pages, Jun. 2000.
Renju Thomas, et al., “Using Dataflow Based Context for Accurate Value Prediction,” 11 pages, Sep. 2001.
Mikko H. Lipasti, et al., “Exceeding the Dataflow Limit via Value Prediction,” Proceedings of the 29thAnnual ACM/IEEE International Symposium of Microarchitecture, Dec. 1996, 12 pages, Dec. 1996.
David M. Gallagher, et al., “Dynamic Memory Disambiguation Using the Memory Conflict Buffer,” Center for Reliable and High-Performance Computing, IL, 13 pages, Oct. 1994.
Glenn Reinman, “Predictive Techniques for Aggressive Load Speculation,” Published in the Proceedings of the Annual 31stInternational Symposium on Microarchitecture, Dec. 1998, 11 pages, Dec. 1998.
Brad Calder, et al., “A Comparative Survey of Load Speculation Architectures,” Journal of Instruction-Level Parallelism I, 2000, pp. 1-39, May 2000.
Filippo Michael A.
Pickett James K.
Advanced Micro Devices , Inc.
Alrobaye Idriss
Chan Eddie P
Kowert Robert C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
LandOfFree
Processor with dependence mechanism to predict whether a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor with dependence mechanism to predict whether a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor with dependence mechanism to predict whether a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4019910