Decoder design adaptable to decode coded signals using min*...

Pulse or digital communications – Receivers – Particular pulse demodulator or detector

Reexamination Certificate

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C375S341000, C714S794000, C714S795000

Reexamination Certificate

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07415079

ABSTRACT:
Decoder design adaptable to decode coded signals using min* or max* processing. A very efficient means of min* processing or max* processing may be performed within a communication device to assist in the very complex and cumbersome calculations that are employed when decoding coded signals. The types of coded signals that may be decoded using min* processing or max* processing are varied, and they include LDPC (Low Density Parity Check) coded signals, turbo coded signals, and TTCM (Turbo Trellis Coded Modulation) coded signals, among other coded signal types. Many of the calculations and/or determinations performed within min* processing or max* processing are performed simultaneously and in parallel of one another thereby ensuring very fast operation. In a finite precision digital implementation, when certain calculated bits of min* or max* processing are available, they govern selection of resultants from among multiple calculations and determinations made simultaneously and in parallel.

REFERENCES:
patent: 2005/0246618 (2005-11-01), Tran et al.
patent: 2005/0262408 (2005-11-01), Tran et al.
patent: 2005/0268206 (2005-12-01), Tran et al.
Zarkeshvari et al. On Implementation of Min-Sum Algorithm For Decoding Low-Density Parity-Check (LDPC) Codes, Nov. 17-21, 2002, IEEE Global Telecommunications Conference, Nov. 17-21, 2002, vol. 2, pp. 1349-1353.
Jianguang et al., On Implementation of Min-Sum Algorithm And Its modifications For Decoding Low-Density Parity-Check (LDPC) Codes, Apr. 2005, vol. 53, Issue 4, pp. 549-554.

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