Bias circuit for power amplifier having a low degradation in...

Details Bias circuit for power amplifier having a low degradation in... Bias circuit for power amplifier having a low degradation in...

2006-11-03

2008-08-26

Nguyen, Khanh V (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S289000

Reexamination Certificate

active

07417507

ABSTRACT:
A combined bias circuit in which a voltage drive bias circuit and a current drive bias circuit are provided in parallel with each other has a configuration in which a linearizer including a first resistor is connected between an amplifying transistor and a second resistor. This configuration ensures that even when a low voltage of 2.4 to 2.5 V is supplied as an external reference voltage, the amplifying operation can be performed while generally constantly maintaining an idling current in a temperature range from a low temperature to a high temperature, and that degradation in distortion characteristics during low-temperature operation can be limited.

REFERENCES:
patent: 6549076 (2003-04-01), Kuriyama
patent: 6946913 (2005-09-01), Moriwaki et al.
patent: 7009453 (2006-03-01), Kuriyama
patent: 2005/0062541 (2005-03-01), Kuriyama
patent: 1 195 890 (2002-04-01), None
patent: 1 515 434 (2005-03-01), None
patent: 11-68469 (1999-03-01), None
patent: 2003-229728 (2003-08-01), None
patent: 2004-343244 (2004-12-01), None
U.S. Appl. No. 11/552,635, filed Oct. 25, 2006, Yamamoto et al.

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