Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2006-05-10
2008-08-12
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S762000, C257S773000, C257SE23141
Reexamination Certificate
active
07411302
ABSTRACT:
There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1of relatively wider area and the second dummy pattern DP2of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1occupy a relatively wide region among the dummy region FA.
REFERENCES:
patent: 4755482 (1988-07-01), Nagakubo
patent: 5569941 (1996-10-01), Takahashi
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 5900655 (1999-05-01), Shim
patent: 5924006 (1999-07-01), Lur et al.
patent: 6153918 (2000-11-01), Kawashima et al.
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 6335560 (2002-01-01), Takeuchi
patent: 6433438 (2002-08-01), Koubuchi et al.
patent: 6495855 (2002-12-01), Sawamura
patent: 6521969 (2003-02-01), Tomita
patent: 6603162 (2003-08-01), Uchiyama et al.
patent: 06-120488 (1994-04-01), None
patent: 10-092921 (1998-04-01), None
patent: 2000-114258 (2000-04-01), None
patent: 2001-144171 (2001-05-01), None
patent: 2001-176959 (2001-06-01), None
Kuroda Kenichi
Watanabe Kozo
Yamamoto Hirohiko
Antonelli, Terry Stout & Kraus, LLP.
Coleman W. David
Hitachi ULSI Systems Co. Ltd.
Renesas Technology Corp.
LandOfFree
Semiconductor device and a method of manufacturing the same... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and a method of manufacturing the same..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and a method of manufacturing the same... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4013660