Duty detection circuit

Details Duty detection circuit Duty detection circuit

2006-02-03

2008-08-12

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000, C327S176000

Reexamination Certificate

active

07411435

ABSTRACT:
A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1through C4in the integration circuit according to this actual frequency.

REFERENCES:
patent: 7199634 (2007-04-01), Cho et al.
patent: 7202722 (2007-04-01), Mahadevan et al.
patent: 2001/0046272 (2001-11-01), Miyano
patent: 2002/0017936 (2002-02-01), Stark et al.
patent: 2004/0041609 (2004-03-01), Lin
patent: 2005/0122149 (2005-06-01), Cho et al.
patent: 61-071715 (1986-04-01), None
patent: 11-127142 (1999-05-01), None
patent: 2000-163961 (2000-06-01), None
patent: 2001-144590 (2001-05-01), None
patent: 2001-156261 (2001-06-01), None
patent: 2001-308698 (2001-11-01), None
patent: 2002-135105 (2002-05-01), None
patent: 2002-344294 (2002-11-01), None
patent: 2003-110411 (2003-04-01), None
patent: 2003-318705 (2003-11-01), None
patent: 2004-015810 (2004-01-01), None
patent: 2004-088679 (2004-03-01), None
patent: 2004-145999 (2004-05-01), None
patent: 2005-0055925 (2005-06-01), None
Korean Office Action issued in Korean Patent Application No. KR 10-2006-0034337, mailed Oct. 23, 2007.
Japanese Office Action, with English translation, issued in Japanese Patent Application No. JP 2005-027483, mailed Jan. 8, 2008.
Japanese Office Action, with partial English translation, issued in Japanese Patent Application No. JP 2005-117750, mailed Nov. 13, 2007.
Ogawa, T., et al., “A 50% duty control for PLL output”, The institute of Electrical Engineers of Japan-Society for the Study of Electronic Circuits, Oct. 19, 2001, pp. 15-19.

Affiliated with

Also associated with

Rating

Duty detection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Duty detection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Duty detection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4009554