Self-aligned, low-resistance, efficient memory array

Details Self-aligned, low-resistance, efficient memory array Self-aligned, low-resistance, efficient memory array

2005-08-29

2008-08-12

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Magnetic field

C257S108000, C257S414000, C257S422000, C257S659000, C438S003000, C438S048000

Reexamination Certificate

active

07411262

ABSTRACT:
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

REFERENCES:
patent: 6413788 (2002-07-01), Tuttle
patent: 6538920 (2003-03-01), Sharma
patent: 6551852 (2003-04-01), Tuttle
patent: 6597049 (2003-07-01), Bhattacharyya
patent: 2002/0160541 (2002-10-01), Durcan et al.

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